LOGICAL RESYNTHESIS OF COMBINATIONAL CIRCUITS FOR RELIABILITY INCREASE
نویسندگان
چکیده
منابع مشابه
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Reduction and for Path Delay Fault Testability Angela Krsti c and Kwang-Ting (Tim) Cheng Department of ECE, University of California, Santa Barbara, CA 93106 Abstract Path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability o...
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ژورنال
عنوان ژورنال: IZVESTIYA SFedU. ENGINEERING SCIENCES
سال: 2020
ISSN: 1999-9429,2311-3103
DOI: 10.18522/2311-3103-2020-4-118-125